1. Field of the Invention
This invention relates to integrated circuit structures, and more particularly to multi-layer integrated circuit structures and methods of forming the same.
2. Description of the Prior Art
In conventional integrated circuit structures, it is necessary to bring a ground wire and a power supply wire to practically every, or every other, transistor in the circuit. The required metallization uses up a large amount of area ("real estate") on the chip, and is also a possible source of cross-talk between different circuits. With high density chips metallization typically occupies 80-90% of the chip's surface area, with power supply and ground wires accounting for a significant portion. In fact, there is a trade-off between real estate and crosstalk; heavier metallizations cause less cross-talk, but take up more real estate. Also, the requirement for ground and power supply wires results in the use of two metallization levels to avoid direct crossovers, with an insulator between each layer. In addition to complicating the fabrication process, the two metallizations can still have a tendency to short through the insulator and can significantly decrease circuit yield.
Silicon-on-insulator (SOI) devices have recently been formed in which a so-called ground plane provides a common source of ground reference throughout the circuit, without the need for separate ground wires. The SOI technique is described in a paper by B. Y. Tsaur, J. C. Fan, M. W. Geis, D. J. Silversmith and R. W. Mountain, "Improved Techniques for Growth of Large-Area Single-Crystal Si Sheets Over SiO.sub.2 Using Lateral Epitaxy by Seeded Solidification," Applied Physics Letters, Vol. 39, Pg. 561-563 (1981). The SOI structure is illustrated in FIG. 1. A bulk silicon substrate 2 is covered with a layer of SiO.sub.2 4, which in turn is covered with a layer of silicon 6 upon which an integrated circuit is fabricated. In FIG. 1, a field effect transistor (FET) is illustrated, with the silicon layer 6 providing a drain 8, source 10 and gate 12 with appropriate doping. An SiO.sub.2 portion 14 is formed over the gate and surmounted by a gate contact 16. The underlying silicon substrate 2 is grounded, and a feed-through connection is provided between the substrate and silicon circuit layer wherever ground potential is desired. In the example shown, the drain 10 is grounded by means of a metallized contact 18 which has been flowed through an opening 20 in the silicon and SiO.sub.2 layers 6, 4 between the drain and substrate 2. Similar ground connects are made to the substrate wherever desired.
The SOI device is formed by providing a layer of amorphous silicon over a single crystal silicon substrate, and separated therefrom by an SiO.sub.2 layer except at one end. The amorphous silicon layer is heated from one end to the other by means of a strip heater, causing the substrate to seed the amorphous layer under the heater so as to recrystallize the amorphous layer into a single crystal. The purpose of the SOI device was to improve the insulation between circuit elements by eliminating the ground wires, and thereby reduce stray capacitance and power consumption while increasing the operating frequency range. The structure was also devised to increase radiation hardness where required.
While an improvement, the SOI structure still devotes a significant amount of real estate to metallization, and is still subject to cross-talk between different components. Also, it still requires two metallization layers. Thus, there is still a need for an integrated circuit structure that solves these problems.